Description
John Wiley FPGA Prototyping by SystemVerilog Examples Xilinx MicroBlaze MCS SoC Edition by Pong P. Chu
A hands-on introduction to FPGA prototyping and SoC design_x000D__x000D__x000D_This is the successor edition of the popular FPGA Prototyping by Verilog Examples text. It follows the same "learning-by-doing" approach to teach the fundamentals and practices of HDL synthesis and FPGA prototyping. The new edition uses a coherent series of examples to demonstrate the process to develop sophisticated digital circuits and IP (intellectual property) cores, integrate them into an SoC (system on a chip) framework, realize the system on an FPGA prototyping board, and verify the hardware and software operation. The examples start with simple gate-level circuits, progress gradually through the RT (register transfer) level modules, and lead to a functional embedded system with custom I/O peripherals and hardware accelerators. Although it is an introductory text, the examples are developed in a rigorous manner, and the derivations follow the strict design guidelines and coding practices used for large, complex digital systems._x000D__x000D__x000D_The book is completely updated and uses the SystemVerilog language, which "absorbs" the Verilog language. It presents the hardware design in the SoC context and introduces the hardware-software co-design concept. Instead of treating examples as isolated entities, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software "programmability" and develop complex and interesting embedded system projects. The new edition:_x000D__x000D__x000D__x000D__x000D__x000D_Adds four general-purpose IP cores, which are multi-channel PWM (pulse width modulation) controller, I2C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller._x000D__x000D_Introduces a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelope generator._x000D__x000D_Expands the original video controller into a complete stream based video subsystem that incorporates a video synchronization circuit, a test-pattern generator, an OSD (on-screen display) controller, a sprite generator, and a frame buffer._x000D__x000D_Provides a detailed discussion on blocking and nonblocking statements and coding styles._x000D__x000D_Describes basic concepts of software-hardware co-design with Xilinx MicroBlaze MCS soft-core processor._x000D__x000D_Provides an overview of bus interconnect and interface circuit._x000D__x000D_Presents basic embedded system software development._x000D__x000D_Suggests additional modules and peripherals for interesting and challenging projects._x000D__x000D__x000D__x000D_FPGA Prototyping by SystemVerilog Examples makes a natural companion text for introductory and advanced digital design courses and embedded system courses. It also serves as an ideal self-teaching guide for practicing engineers who wish to learn more about this emerging area of interest._x000D_ Table of contents :- _x000D_
Preface xxvii_x000D_
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Acknowledgments xxxiii_x000D_
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PART I BASIC DIGITAL CIRCUITS DEVELOPMENT_x000D_
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1 Gate-Level Combinational Circuit 1_x000D_
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1.1 Introduction 1_x000D_
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1.1.1 Brief history of Verilog and SystemVerilog 1_x000D_
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1.1.2 Book coverage 2_x000D_
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1.2 General description 3_x000D_
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1.3 Basic lexical elements and data types 4_x000D_
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1.3.1 Lexical elements 4_x000D_
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1.3.2 Data types used in the book 5_x000D_
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1.3.3 Number representation 6_x000D_
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1.3.4 Operators 7_x000D_
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1.4 Program skeleton 7_x000D_
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1.4.1 Port declaration 7_x000D_
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1.4.2 Signal declaration 8_x000D_
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1.4.3 Program body 8_x000D_
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1.4.4 Concurrent semantics 9_x000D_
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1.4.5 Another example 10_x000D_
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1.5 Structural description 10_x000D_
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1.6 Top-level signal mapping 13_x000D_
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1.7 Testbench 14_x000D_
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1.8 Bibliographic notes 16_x000D_
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1.9 Suggested experiments 16_x000D_
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1.9.1 Code for gate-level greater-than circuit 17_x000D_
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1.9.2 Code for gate-level binary decoder 17_x000D_
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2 Overview of FPGA and EDA Software 19_x000D_
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2.1 FPGA 19_x000D_
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2.1.1 Overview of a general FPGA device 19_x000D_
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2.1.2 Overview of the Xilinx Artix-7 devices 20_x000D_
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2.2 Overview of the Digilent Nexys 4 DDR board 21_x000D_
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2.3 Development flow 22_x000D_
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2.4 Xilinx Vivado Design Suite 24_x000D_
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2.5 Bibliographic notes 24_x000D_
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2.6 Suggested experiments 24_x000D_
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2.6.1 Gate-level greater-than circuit 24_x000D_
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2.6.2 Gate-level binary decoder 26_x000D_
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3 RT-Level Combinational Circuit 29_x000D_
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3.1 Operators 29_x000D_
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3.1.1 Arithmetic operators 31_x000D_
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3.1.2 Shift operators 31_x000D_
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3.1.3 Relational and equality operators 32_x000D_
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3.1.4 Bitwise, reduction, and logical operators 32_x000D_
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3.1.5 Concatenation and replication operators 33_x000D_
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3.1.6 Conditional operators 34_x000D_
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3.1.7 Operator precedence 35_x000D_
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3.1.8 Expression bit-length adjustment 35_x000D_
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3.1.9 Synthesis of z and x values 36_x000D_
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3.2 Always block for a combinational circuit 38_x000D_
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3.2.1 Overview of always block 39_x000D_
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3.2.2 Procedural assignment 40_x000D_
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3.2.3 Conceptual examples 40_x000D_
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3.3 Coding guidelines 43_x000D_
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3.4 If statement 43_x000D_
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3.4.1 Syntax 43_x000D_
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3.4.2 Examples 44_x000D_
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3.5 Case statement 45_x000D_
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3.5.1 Syntax 45_x000D_
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3.5.2 Examples 46_x000D_
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3.5.3 The casez and casex statements 47_x000D_
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3.5.4 Full case and parallel case 48_x000D_
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3.6 Routing structure of conditional control constructs 49_x000D_
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3.6.1 Priority routing network 49_x000D_
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3.6.2 Multiplexing network 51_x000D_
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3.7 Additional coding guidelines for an always block 52_x000D_
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3.7.1 Common errors in combinational circuit codes 52_x000D_
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3.7.2 Guidelines 56_x000D_
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3.8 Parameter and constant 56_x000D_
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3.8.1 Constant 56_x000D_
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3.8.2 Parameter 58_x000D_
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3.9 Replicated structure 59_x000D_
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3.9.1 Generate-for statement 59_x000D_
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3.9.2 Procedural-for statement 60_x000D_
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3.9.3 Example 60_x000D_
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3.10 Design examples 62_x000D_
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3.10.1 Hexadecimal digit to seven-segment LED decoder 62_x000D_
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3.10.2 Sign-magnitude adder 65_x000D_
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3.10.3 Barrel shifter 68_x000D_
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3.10.4 Simplified floating-point adder 69_x000D_
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3.11 Bibliographic notes 73_x000D_
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3.12 Suggested experiments 73_x000D_
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3.12.1 Multi-function barrel shifter 73_x000D_
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3.12.2 Parameterized barrel shifter 74_x000D_
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3.12.3 Dual-priority encoder 74_x000D_
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3.12.4 BCD incrementor 74_x000D_
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3.12.5 Floating-point greater-than circuit 74_x000D_
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3.12.6 Floating-point and signed integer conversion circuit 74_x000D_
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3.12.7 Enhanced floating-point adder 75_x000D_
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4 Regular Sequential Circuit 77_x000D_
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4.1 Introduction 77_x000D_
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4.1.1 D FF and register 78_x000D_
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4.1.2 Basic block system 78_x000D_
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4.1.3 Code development 79_x000D_
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4.1.4 Sequential circuit coding guidelines and style 79_x000D_
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4.2 HDL code of the FF and register 80_x000D_
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4.2.1 D FF 80_x000D_
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4.2.2 Register 85_x000D_
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4.3 Simple design examples 85_x000D_
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4.3.1 Shift register 85_x000D_
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4.3.2 Binary counter and variant 87_x000D_
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4.4 Testbench for sequential circuits 89_x000D_
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4.5 Case study 93_x000D_
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4.5.1 LED time-multiplexing circuit 93_x000D_
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4.5.2 Stopwatch 101_x000D_
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4.6 Timing and clocking 104_x000D_
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4.6.1 Timing of FF 104_x000D_
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4.6.2 Maximum operating frequency 104_x000D_
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4.6.3 Clock tree 107_x000D_
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4.6.4 GALS system and CDC 107_x000D_
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4.7 Bibliographic notes 108_x000D_
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4.8 Suggested experiments 108_x000D_
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4.8.1 Programmable square wave generator 108_x000D_
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4.8.2 PWM and LED dimmer 108_x000D_
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4.8.3 Rotating square circuit 109_x000D_
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4.8.4 Heartbeat circuit 109_x000D_
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4.8.5 Rotating LED banner circuit 109_x000D_
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4.8.6 Enhanced stopwatch 110_x000D_
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5 FSM 111_x000D_
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5.1 Introduction 111_x000D_
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5.1.1 Mealy and Moore outputs 112_x000D_
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5.1.2 FSM representation 112_x000D_
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5.2 FSM code development 115_x000D_
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5.2.1 Enumerated data type and state assignment 115_x000D_
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5.2.2 Multi-segment code 116_x000D_
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5.2.3 Two-segment code 117_x000D_
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5.3 Design examples 118_x000D_
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5.3.1 Rising-edge detector 118_x000D_
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5.3.2 Debouncing circuit 123_x000D_
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5.3.3 Testing circuit 126_x000D_
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5.4 Bibliographic notes 128_x000D_
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5.5 Suggested experiments 128_x000D_
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5.5.1 Dual-edge detector 128_x000D_
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5.5.2 Early detection debouncing circuit 128_x000D_
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5.5.3 Parking lot occupancy counter 129_x000D_
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6 FSMD 131_x000D_
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6.1 Introduction 131_x000D_
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6.1.1 Single RT operation 132_x000D_
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6.1.2 ASMD chart 132_x000D_
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6.1.3 Decision box with a register 134_x000D_
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6.2 Code development of an FSMD 137_x000D_
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6.2.1 Debouncing circuit based on RT methodology 137_x000D_
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6.2.2 Code with explicit data path components 137_x000D_
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6.2.3 Code with implicit data path components 140_x000D_
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6.2.4 Comparison 142_x000D_
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6.3 Design examples 144_x000D_
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6.3.1 Fibonacci number circuit 144_x000D_
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6.3.2 Division circuit 147_x000D_
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6.3.3 Binary-to-BCD conversion circuit 150_x000D_
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6.3.4 Period counter 153_x000D_
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6.3.5 Accurate low-frequency counter 156_x000D_
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6.4 Bibliographic notes 159_x000D_
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6.5 Suggested experiments 159_x000D_
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6.5.1 Early detection debouncing circuit 159_x000D_
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6.5.2 BCD-to-binary conversion circuit 160_x000D_
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6.5.3 Fibonacci circuit with BCD I/O: design approach 1 160_x000D_
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6.5.4 Fibonacci circuit with BCD I/O: design approach 2 160_x000D_
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6.5.5 Auto-scaled low-frequency counter 161_x000D_
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6.5.6 Reaction timer 161_x000D_
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6.5.7 Babbage difference engine emulation circuit 162_x000D_
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7 RAM and Buffer of FPGA 165_x000D_
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7.1 Embedded memory of FPGA device 165_x000D_
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7.1.1 Memory of an Artix device 166_x000D_
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7.1.2 Memory available in the Nexys 4 DDR board 166_x000D_
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7.2 General description for a RAM-like component 167_x000D_
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7.2.1 Register file 167_x000D_
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7.2.2 Dynamic array indexing operation 169_x000D_
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7.2.3 Key aspects of a RAM module 170_x000D_
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7.2.4 Genuine ROM 171_x000D_
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7.3 FIFO buffer 173_x000D_
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7.3.1 FIFO read configuration 174_x000D_
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7.3.2 Circular queue implementation 175_x000D_
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7.4 HDL templates for memory inference 178_x000D_
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7.4.1 Methods to incorporate memory modules 178_x000D_
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7.4.2 Synchronous dual-port RAM 179_x000D_
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7.4.3 "Simple" synchronous dual-port RAM 180_x000D_
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7.4.4 Synchronous single-port RAM 181_x000D_
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7.4.5 Synchronous ROM 182_x000D_
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7.4.6 BRAM-based FIFO buffer 183_x000D_
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7.4.7 Design considerations 183_x000D_
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7.5 Overview of memory controller 184_x000D_
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7.6 Bibliographic notes 185_x000D_
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7.7 Suggested experiments 186_x000D_
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7.7.1 ROM-based sign-magnitude adder 186_x000D_
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7.7.2 ROM-based temperature conversion 186_x000D_
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7.7.3 FIFO with data width conversion 186_x000D_
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7.7.4 Standard FIFO to FWFT FIFO conversion circuit 187_x000D_
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7.7.5 FIFO buffer with extended status 187_x000D_
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7.7.6 Stack 187_x000D_
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8 Selected Topics of SystemVerilog 189_x000D_
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8.1 Timing model 189_x000D_
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8.1.1 Concurrent constructs 190_x000D_
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8.1.2 Assignment statement 190_x000D_
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8.1.3 Basic model 190_x000D_
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8.1.4 Blocking versus nonblocking assignment 192_x000D_
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8.2 Coding guidelines revisited 194_x000D_
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8.2.1 "Single variable assignment" guideline 195_x000D_
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8.2.2 "Blocking assignment for combinational circuit" guideline 195_x000D_
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8.2.3 "Nonblocking assignment for register" guideline 197_x000D_
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8.3 Alternative coding style 198_x000D_
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8.3.1 First coding style revisited 198_x000D_
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8.3.2 Sequential circuit with mixed blocking and nonblocking assignments 199_x000D_
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8.3.3 Combined coding style 201_x000D_
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8.3.4 Summary 206_x000D_
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8.4 Data types 206_x000D_
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8.4.1 The net and variable types 206_x000D_
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8.4.2 The logic data type 207_x000D_
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8.4.3 Limitation of the logic data type 208_x000D_
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8.4.4 New data types in SystemVerilog 208_x000D_
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8.5 Use of the signed data type 209_x000D_
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8.5.1 Overview 209_x000D_
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8.5.2 Signed number conversion 210_x000D_
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8.6 Bibliographic notes 211_x000D_
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8.7 Suggested experiments 211_x000D_
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8.7.1 Shift register with blocking and nonblocking assignments 211_x000D_
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8.7.2 Alternative coding style for the BCD counter 212_x000D_
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8.7.3 Alternative coding style for the FIFO buffer 212_x000D_
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8.7.4 Alternative coding style for the Fibonacci circuit 212_x000D_
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8.7.5 Dual-mode comparator 212_x000D_
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PART II EMBEDDED SOC I: VANILLA FPRO SYSTEM_x000D_
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9 Overview of Embedded SoC Systems 215_x000D_
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9.1 Embedded SoC 215_x000D_
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9.1.1 Overview of embedded systems 215_x000D_
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9.1.2 FPGA-based SoC 216_x000D_
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9.1.3 IP cores 216_x000D_
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9.2 Development flow of the embedded SoC 217_x000D_
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9.2.1 Hardware-software partition 217_x000D_
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9.2.2 Hardware development flow 217_x000D_
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9.2.3 Software development flow 219_x000D_
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9.2.4 Physical implementation and test 219_x000D_
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9.2.5 Custom IP core development 219_x000D_
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9.3 FPro SoC Platform 220_x000D_
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9.3.1 Motivations 220_x000D_
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9.3.2 Platform hardware organization 221_x000D_
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9.3.3 Platform software organization 223_x000D_
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9.3.4 Modified development flow 224_x000D_
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9.4 Adaptation on the Digilent Nexys 4 DDR board 224_x000D_
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9.5 Portability 226_x000D_
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9.5.1 Processor Module and Bridge 226_x000D_
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9.5.2 MMIO subsystem 227_x000D_
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9.5.3 Video subsystem 227_x000D_
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9.6 Organization 228_x000D_
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9.7 Bibliographic notes 228_x000D_
_x000D_
_x000D_
10 Bare Metal System Software Development 231_x000D_
_x000D_
_x000D_
10.1 Bare metal system development overview 231_x000D_
_x000D_
_x000D_
10.1.1 Desktop-like system versus bare metal system 231_x000D_
_x000D_
_x000D_
10.1.2 Basic embedded program architecture 232_x000D_
_x000D_
_x000D_
10.2 Memory-mapped I/O 233_x000D_
_x000D_
_x000D_
10.2.1 Overview 233_x000D_
_x000D_
_x000D_
10.2.2 Memory alignment 234_x000D_
_x000D_
_x000D_
10.2.3 I/O register map 234_x000D_
_x000D_
_x000D_
10.2.4 I/O address space of the FPro system 234_x000D_
_x000D_
_x000D_
10.3 Direct I/O Register Access 235_x000D_
_x000D_
_x000D_
10.3.1 Review of C pointer 235_x000D_
_x000D_
_x000D_
10.3.2 C pointer for I/O register 236_x000D_
_x000D_
_x000D_
10.4 Robust I/O register access 237_x000D_
_x000D_
_x000D_
10.4.1 chu_io_map.h and chu_io_map.svh 237_x000D_
_x000D_
_x000D_
10.4.2 inttypes.h 238_x000D_
_x000D_
_x000D_
10.4.3 chu_io_rw.h 239_x000D_
_x000D_
_x000D_
10.5 Techniques for low-level I/O operations 241_x000D_
_x000D_
_x000D_
10.5.1 Bit manipulation 241_x000D_
_x000D_
_x000D_
10.5.2 Packing and unpacking 242_x000D_
_x000D_
_x000D_
10.6 Device Drivers 243_x000D_
_x000D_
_x000D_
10.6.1 Overview 243_x000D_
_x000D_
_x000D_
10.6.2 GPO and GPI drivers 243_x000D_
_x000D_
_x000D_
10.6.3 Timer driver 245_x000D_
_x000D_
_x000D_
10.6.4 UART driver 247_x000D_
_x000D_
_x000D_
10.7 FPro utility routines and directory structure 248_x000D_
_x000D_
_x000D_
10.7.1 Minimal hardware requirements 248_x000D_
_x000D_
_x000D_
10.7.2 Utility routines 248_x000D_
_x000D_
_x000D_
10.7.3 Directory structure 251_x000D_
_x000D_
_x000D_
10.8 Test program 252_x000D_
_x000D_
_x000D_
10.8.1 IP core verification routine 252_x000D_
_x000D_
_x000D_
10.8.2 Programming with limited memory 252_x000D_
_x000D_
_x000D_
10.8.3 Test function integration 252_x000D_
_x000D_
_x000D_
10.8.4 Test program for the vanilla FPro system 253_x000D_
_x000D_
_x000D_
10.8.5 Implementation 254_x000D_
_x000D_
_x000D_
10.9 Bibliographic notes 255_x000D_
_x000D_
_x000D_
10.10 Suggested experiments 255_x000D_
_x000D_
_x000D_
10.10.1 Chasing LEDs 255_x000D_
_x000D_
_x000D_
10.10.2 Collision LEDs 256_x000D_
_x000D_
_x000D_
10.10.3 Pulse width modulation 256_x000D_
_x000D_
_x000D_
10.10.4 System time display 256_x000D_
_x000D_
_x000D_
11 FPro Bus Protocol and MMIO Slot Specification 257_x000D_
_x000D_
_x000D_
11.1 FPro bus 257_x000D_
_x000D_
_x000D_
11.1.1 Overview of the bus 257_x000D_
_x000D_
_x000D_
11.1.2 SoC interconnect 258_x000D_
_x000D_
_x000D_
11.1.3 FPro bus protocol specification 259_x000D_
_x000D_
_x000D_
11.2 Interface with the bus 260_x000D_
_x000D_
_x000D_
11.2.1 Introduction 260_x000D_
_x000D_
_x000D_
11.2.2 Write interface and decoding 261_x000D_
_x000D_
_x000D_
11.2.3 Read interface and multiplexing 263_x000D_
_x000D_
_x000D_
11.2.4 FIFO buffer as an I/O register 264_x000D_
_x000D_
_x000D_
11.2.5 Timing consideration 265_x000D_
_x000D_
_x000D_
11.3 MMIO I/O core 266_x000D_
_x000D_
_x000D_
11.3.1 MMIO slot interface specification 266_x000D_
_x000D_
_x000D_
11.3.2 Basic MMIO I/O core construction 268_x000D_
_x000D_
_x000D_
11.3.3 GPO and GPI cores 269_x000D_
_x000D_
_x000D_
11.4 Timer core development 270_x000D_
_x000D_
_x000D_
11.4.1 Custom logic 270_x000D_
_x000D_
_x000D_
11.4.2 Register map 271_x000D_
_x000D_
_x000D_
11.4.3 Wrapping circuit for the slot interface 271_x000D_
_x000D_
_x000D_
11.5 MMIO controller 272_x000D_
_x000D_
_x000D_
11.5.1 chu_io_map.svh file 273_x000D_
_x000D_
_x000D_
11.5.2 HDL code 273_x000D_
_x000D_
_x000D_
11.5.3 Vanilla MMIO subsystem 275_x000D_
_x000D_
_x000D_
11.6 MCS I/O bus and bridge 278_x000D_
_x000D_
_x000D_
11.6.1 Overview of Xilinx MicroBlaze MCS 278_x000D_
_x000D_
_x000D_
11.6.2 MicroBlaze MCS I/O bus 278_x000D_
_x000D_
_x000D_
11.6.3 MCS-to-FPro bridge 279_x000D_
_x000D_
_x000D_
11.7 Vanilla FPro system construction 281_x000D_
_x000D_
_x000D_
11.8 Bibliographic notes 282_x000D_
_x000D_
_x000D_
11.9 Suggested experiments 283_x000D_
_x000D_
_x000D_
11.9.1 FPro bus with a byte-lane enable signal 283_x000D_
_x000D_
_x000D_
11.9.2 Seven-segment control with a GPO core 283_x000D_
_x000D_
_x000D_
11.9.3 GPIO core 283_x000D_
_x000D_
_x000D_
11.9.4 Blinking-LED core 284_x000D_
_x000D_
_x000D_
11.9.5 Timer core with a programmable period 284_x000D_
_x000D_
_x000D_
11.9.6 Timer core with a run-once mode 284_x000D_
_x000D_
_x000D_
12 UART Core 287_x000D_
_x000D_
_x000D_
12.1 Introduction 287_x000D_
_x000D_
_x000D_
12.1.1 Overview of serial communication 287_x000D_
_x000D_
_x000D_
12.1.2 Overview of the UART 288_x000D_
_x000D_
_x000D_
12.1.3 Oversampling procedure 288_x000D_
_x000D_
_x000D_
12.2 UART construction 289_x000D_
_x000D_
_x000D_
12.2.1 Conceptual design 289_x000D_
_x000D_
_x000D_
12.2.2 Baud rate generator 290_x000D_
_x000D_
_x000D_
12.2.3 UART receiver 291_x000D_
_x000D_
_x000D_
12.2.4 UART transmitter 293_x000D_
_x000D_
_x000D_
12.2.5 Top-level HDL code 295_x000D_
_x000D_
_x000D_
12.3 UART core development 296_x000D_
_x000D_
_x000D_
12.3.1 Register map 296_x000D_
_x000D_
_x000D_
12.3.2 Wrapping circuit for the slot interface 297_x000D_
_x000D_
_x000D_
12.4 UART driver 298_x000D_
_x000D_
_x000D_
12.4.1 Class definition 299_x000D_
_x000D_
_x000D_
12.4.2 Basic methods 300_x000D_
_x000D_
_x000D_
12.4.3 ASCII code 301_x000D_
_x000D_
_x000D_
12.4.4 Display methods 303_x000D_
_x000D_
_x000D_
12.4.5 Test 305_x000D_
_x000D_
_x000D_
12.5 Additional project ideas 305_x000D_
_x000D_
_x000D_
12.5.1 Original serial port 305_x000D_
_x000D_
_x000D_
12.5.2 Emulated serial port 305_x000D_
_x000D_
_x000D_
12.5.3 Direct connection 306_x000D_
_x000D_
_x000D_
12.5.4 USB-to-UART adaptor 306_x000D_
_x000D_
_x000D_
12.5.5 Wireless adaptor 307_x000D_
_x000D_
_x000D_
12.6 Bibliographic notes 308_x000D_
_x000D_
_x000D_
12.7 Suggested experiments 308_x000D_
_x000D_
_x000D_
12.7.1 UART-controlled chasing LEDs 308_x000D_
_x000D_
_x000D_
12.7.2 Alternative read configuration 308_x000D_
_x000D_
_x000D_
12.7.3 UART controller with a parity bit 308_x000D_
_x000D_
_x000D_
12.7.4 UART core with an error status 309_x000D_
_x000D_
_x000D_
12.7.5 Configurable UART core 309_x000D_
_x000D_
_x000D_
12.7.6 UART core with automatic baud rate detection 309_x000D_
_x000D_
_x000D_
12.7.7 UART core with enhanced automatic baud rate detection 310_x000D_
_x000D_
_x000D_
12.7.8 UART core with an automatic baud rate and a parity detection circuit 310_x000D_
_x000D_
_x000D_
PART III EMBEDDED SOC II: BASIC I/O CORES_x000D_
_x000D_
_x000D_
13 Xilinx XADC Core 313_x000D_
_x000D_
_x000D_
13.1 Overview of XADC 313_x000D_
_x000D_
_x000D_
13.1.1 Block diagram 313_x000D_
_x000D_
_x000D_
13.1.2 Configuration 314_x000D_
_x000D_
_x000D_
13.2 XADC core development 315_x000D_
_x000D_
_x000D_
13.2.1 XADC instantiation 315_x000D_
_x000D_
_x000D_
13.2.2 Basic wrapping circuit design 316_x000D_
_x000D_
_x000D_
13.2.3 Register map 318_x000D_
_x000D_
_x000D_
13.2.4 HDL code 318_x000D_
_x000D_
_x000D_
13.3 XADC core device driver 320_x000D_
_x000D_
_x000D_
13.3.1 Class definition 320_x000D_
_x000D_
_x000D_
13.3.2 Class implementation 321_x000D_
_x000D_
_x000D_
13.3.3 Testing for the XADC core 322_x000D_
_x000D_
_x000D_
13.4 Sampler FPro system 323_x000D_
_x000D_
_x000D_
13.4.1 Testing procedure of an FPro core 323_x000D_
_x000D_
_x000D_
13.4.2 System configuration 323_x000D_
_x000D_
_x000D_
13.4.3 Hardware derivation 324_x000D_
_x000D_
_x000D_
13.4.4 Software verification program 331_x000D_
_x000D_
_x000D_
13.5 Additional project ideas 332_x000D_
_x000D_
_x000D_
13.6 Bibliographic notes 333_x000D_
_x000D_
_x000D_
13.7 Suggested experiments 333_x000D_
_x000D_
_x000D_
13.7.1 Real-time voltage display 333_x000D_
_x000D_
_x000D_
13.7.2 Potentiometer-controlled chasing LEDs 333_x000D_
_x000D_
_x000D_
13.7.3 Potentiometer-controlled LED dimmer 333_x000D_
_x000D_
_x000D_
13.7.4 Enhanced wrapping circuit: part I 333_x000D_
_x000D_
_x000D_
13.7.5 Enhanced wrapping circuit: part II 333_x000D_
_x000D_
_x000D_
14 Pulse Width Modulation Core 335_x000D_
_x000D_
_x000D_
14.1 Introduction 335_x000D_
_x000D_
_x000D_
14.1.1 PWM as analog output 335_x000D_
_x000D_
_x000D_
14.1.2 Main characteristics 336_x000D_
_x000D_
_x000D_
14.2 PWM design 336_x000D_
_x000D_
_x000D_
14.2.1 Basic design 336_x000D_
_x000D_
_x000D_
14.2.2 Enhanced design 337_x000D_
_x000D_
_x000D_
14.3 PWM core development 339_x000D_
_x000D_
_x000D_
14.3.1 Register map 339_x000D_
_x000D_
_x000D_
14.3.2 Wrapped PWM circuit 340_x000D_
_x000D_
_x000D_
14.4 PWM driver 341_x000D_
_x000D_
_x000D_
14.4.1 Class definition 341_x000D_
_x000D_
_x000D_
14.4.2 Class implementation 342_x000D_
_x000D_
_x000D_
14.5 Testing 343_x000D_
_x000D_
_x000D_
14.6 Project ideas 343_x000D_
_x000D_
_x000D_
14.7 Suggested experiments 345_x000D_
_x000D_
_x000D_
14.7.1 Police dash light 345_x000D_
_x000D_
_x000D_
14.7.2 Rainbow night light 345_x000D_
_x000D_
_x000D_
14.7.3 Enhanced PWM core: part I 345_x000D_
_x000D_
_x000D_
14.7.4 Enhanced PWM core: part II 346_x000D_
_x000D_
_x000D_
14.7.5 Enhanced GPIO core 346_x000D_
_x000D_
_x000D_
14.7.6 Servo motor driver 346_x000D_
_x000D_
_x000D_
15 Debouncing Core and LED-Mux Core 347_x000D_
_x000D_
_x000D_
15.1 Debouncing Core 347_x000D_
_x000D_
_x000D_
15.1.1 Multi-bit debouncing circuit 347_x000D_
_x000D_
_x000D_
15.1.2 Register map and the slot wrapping circuit 350_x000D_
_x000D_
_x000D_
15.1.3 Driver 351_x000D_
_x000D_
_x000D_
15.1.4 Test 352_x000D_
_x000D_
_x000D_
15.2 LED-mux core 352_x000D_
_x000D_
_x000D_
15.2.1 Eight-digit seven-segment LED display multiplexing circuit 352_x000D_
_x000D_
_x000D_
15.2.2 Register map and the slot wrapping circuit 354_x000D_
_x000D_
_x000D_
15.2.3 Driver 355_x000D_
_x000D_
_x000D_
15.2.4 Test 358_x000D_
_x000D_
_x000D_
15.3 Project ideas 358_x000D_
_x000D_
_x000D_
15.4 Suggested experiments 360_x000D_
_x000D_
_x000D_
15.4.1 Area comparison of two debouncing circuits 360_x000D_
_x000D_
_x000D_
15.4.2 Enhanced debouncing core: part I 360_x000D_
_x000D_
_x000D_
15.4.3 Enhanced debouncing core: part II 360_x000D_
_x000D_
_x000D_
15.4.4 Rotating square pattern revisited 360_x000D_
_x000D_
_x000D_
15.4.5 Heartbeat pattern revisited 360_x000D_
_x000D_
_x000D_
15.4.6 Stopwatch 360_x000D_
_x000D_
_x000D_
15.4.7 Enhanced LED-mux core 361_x000D_
_x000D_
_x000D_
16 SPI Core 363_x000D_
_x000D_
_x000D_
16.1 Overview 363_x000D_
_x000D_
_x000D_
16.1.1 Conceptual architecture 364_x000D_
_x000D_
_x000D_
16.1.2 Multiple-device configuration 364_x000D_
_x000D_
_x000D_
16.1.3 Basic timing 366_x000D_
_x000D_
_x000D_
16.1.4 Operation modes 367_x000D_
_x000D_
_x000D_
16.1.5 Undefined aspects 368_x000D_
_x000D_
_x000D_
16.2 SPI controller 369_x000D_
_x000D_
_x000D_
16.2.1 Basic design 369_x000D_
_x000D_
_x000D_
16.2.2 FSMD construction 370_x000D_
_x000D_
_x000D_
16.2.3 HDL implementation 370_x000D_
_x000D_
_x000D_
16.3 SPI core development 374_x000D_
_x000D_
_x000D_
16.3.1 Register map 374_x000D_
_x000D_
_x000D_
16.3.2 Wrapping circuit for the slot interface 374_x000D_
_x000D_
_x000D_
16.4 SPI driver 376_x000D_
_x000D_
_x000D_
16.4.1 Class definition 376_x000D_
_x000D_
_x000D_
16.4.2 Class implementation 377_x000D_
_x000D_
_x000D_
16.5 Test 378_x000D_
_x000D_
_x000D_
16.5.1 ADXL362 accelerometer 378_x000D_
_x000D_
_x000D_
16.5.2 Test program 380_x000D_
_x000D_
_x000D_
16.6 Project ideas 381_x000D_
_x000D_
_x000D_
16.6.1 SD card 381_x000D_
_x000D_
_x000D_
16.6.2 TFT LCD module 382_x000D_
_x000D_
_x000D_
16.7 Bibliographic notes 382_x000D_
_x000D_
_x000D_
16.8 Suggested experiments 382_x000D_
_x000D_
_x000D_
16.8.1 Inclination sensing 382_x000D_
_x000D_
_x000D_
16.8.2 "Tapping" detection 382_x000D_
_x000D_
_x000D_
16.8.3 ADXL362 C++ class 383_x000D_
_x000D_
_x000D_
16.8.4 Enhanced SPI controller: part I 383_x000D_
_x000D_
_x000D_
16.8.5 Enhanced SPI controller: part II 383_x000D_
_x000D_
_x000D_
16.8.6 "Automatic-read" ADXL362 wrapper: part I 383_x000D_
_x000D_
_x000D_
16.8.7 "Automatic-read" ADXL362 wrapper: part II 384_x000D_
_x000D_
_x000D_
16.8.8 Flash memory access 384_x000D_
_x000D_
_x000D_
16.8.9 SPI slave controller: part I 384_x000D_
_x000D_
_x000D_
16.8.10 SPI slave controller: part II 385_x000D_
_x000D_
_x000D_
17 I2C Core 387_x000D_
_x000D_
_x000D_
17.1 Overview 387_x000D_
_x000D_
_x000D_
17.1.1 Electrical characteristics 388_x000D_
_x000D_
_x000D_
17.1.2 Basic bus protocol 388_x000D_
_x000D_
_x000D_
17.1.3 Basic timing 389_x000D_
_x000D_
_x000D_
17.1.4 Additional features 390_x000D_
_x000D_
_x000D_
17.2 I2C controller 391_x000D_
_x000D_
_x000D_
17.2.1 Basic design 391_x000D_
_x000D_
_x000D_
17.2.2 Conceptual FSMD construction 391_x000D_
_x000D_
_x000D_
17.2.3 Output control logic 394_x000D_
_x000D_
_x000D_
17.2.4 I2C bus clock generation 394_x000D_
_x000D_
_x000D_
17.2.5 HDL implementation 395_x000D_
_x000D_
_x000D_
17.3 I2C core development 400_x000D_
_x000D_
_x000D_
17.3.1 Register map 400_x000D_
_x000D_
_x000D_
17.3.2 Wrapping circuit for the slot interface 400_x000D_
_x000D_
_x000D_
17.4 I2C driver 401_x000D_
_x000D_
_x000D_
17.4.1 Class definition 401_x000D_
_x000D_
_x000D_
17.4.2 Class implementation 402_x000D_
_x000D_
_x000D_
17.5 Test 405_x000D_
_x000D_
_x000D_
17.5.1 ADT7420 temperature sensor 405_x000D_
_x000D_
_x000D_
17.5.2 Test program 406_x000D_
_x000D_
_x000D_
17.6 Project idea 406_x000D_
_x000D_
_x000D_
17.7 Bibliographic notes 407_x000D_
_x000D_
_x000D_
17.8 Suggested experiments 407_x000D_
_x000D_
_x000D_
17.8.1 Thermometer 407_x000D_
_x000D_
_x000D_
17.8.2 ADT7420 C++ class 407_x000D_
_x000D_
_x000D_
17.8.3 Enhanced I2C core 408_x000D_
_x000D_
_x000D_
17.8.4 "Automatic-read" ADT7420 wrapper 408_x000D_
_x000D_
_x000D_
17.8.5 I2C slave controller: part I 408_x000D_
_x000D_
_x000D_
17.8.6 I2C slave controller: part II 408_x000D_
_x000D_
_x000D_
18 PS2 Core 409_x000D_
_x000D_
_x000D_
18.1 Introduction 409_x000D_
_x000D_
_x000D_
18.1.1 PS2-device-to-host communication protocol and timing 410_x000D_
_x000D_
_x000D_
18.1.2 Host-to-PS2-device communication protocol and timing 410_x000D_
_x000D_
_x000D_
18.2 PS2 controller 411_x000D_
_x000D_
_x000D_
18.2.1 Conceptual design 411_x000D_
_x000D_
_x000D_
18.2.2 PS2 receiving subsystem 411_x000D_
_x000D_
_x000D_
18.2.3 PS2 transmitting subsystem 415_x000D_
_x000D_
_x000D_
18.2.4 Complete PS2 system 419_x000D_
_x000D_
_x000D_
18.3 PS2 core development 420_x000D_
_x000D_
_x000D_
18.3.1 Register map 420_x000D_
_x000D_
_x000D_
18.3.2 Wrapping circuit for the slot interface 421_x000D_
_x000D_
_x000D_
18.4 PS2 driver 422_x000D_
_x000D_
_x000D_
18.4.1 Class definition 422_x000D_
_x000D_
_x000D_
18.4.2 Lower layer methods 422_x000D_
_x000D_
_x000D_
18.4.3 PS2 initialization routine 423_x000D_
_x000D_
_x000D_
18.4.4 Keyboard routine 425_x000D_
_x000D_
_x000D_
18.4.5 Mouse routine 428_x000D_
_x000D_
_x000D_
18.5 Test 430_x000D_
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18.6 Bibliographic notes 431_x000D_
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18.7 Suggested experiments 431_x000D_
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18.7.1 PS2 receiving subsystem with watchdog timer 431_x000D_
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18.7.2 Keyboard-controlled LED flashing circuit 432_x000D_
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18.7.3 Enhanced keyboard driver routine: part I 432_x000D_
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18.7.4 Enhanced keyboard driver routine: part II 432_x000D_
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18.7.5 Remote-mode mouse driver 432_x000D_
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18.7.6 Scroll-wheel mouse driver 432_x000D_
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19 Sound I: DDFS Core 433_x000D_
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19.1 Introduction 433_x000D_
_x000D_
_x000D_
19.2 Design and implementation 434_x000D_
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19.2.1 Direct synthesis of a digital waveform 434_x000D_
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19.2.2 Direct synthesis of an unmodulated analog waveform 435_x000D_
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19.2.3 Direct synthesis of a modulated analog waveform 436_x000D_
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19.3 Fixed-point arithmetic 437_x000D_
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19.4 DDFS construction 438_x000D_
_x000D_
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19.5 DAC (digital-to-analog converter) 440_x000D_
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19.5.1 Conceptual design 440_x000D_
_x000D_
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19.5.2 HDL implementation 441_x000D_
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19.6 DDFS core development 442_x000D_
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19.6.1 Register map 442_x000D_
_x000D_
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19.6.2 Wrapping circuit for the slot interface 443_x000D_
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19.7 DDFS driver 444_x000D_
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19.7.1 Class definition 444_x000D_
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19.7.2 Class implementation 445_x000D_
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19.8 Test 447_x000D_
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19.9 Bibliographic notes 448_x000D_
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19.10 Suggested experiments 448_x000D_
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19.10.1 Quadrature phase carrier generation 448_x000D_
_x000D_
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19.10.2 Reduced-size phase-to-amplitude lookup table 448_x000D_
_x000D_
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19.10.3 Additive harmonic synthesis 449_x000D_
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19.10.4 Simple function generator 449_x000D_
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19.10.5 Arbitrary waveform generator 449_x000D_
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19.10.6 Sample-based synthesis 449_x000D_
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20 Sound II: ADSR Core 451_x000D_
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20.1 Introduction 451_x000D_
_x000D_
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20.2 ADSR envelope generator 452_x000D_
_x000D_
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20.2.1 Conceptual FSMD design 453_x000D_
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20.2.2 ASMD chart 453_x000D_
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20.2.3 HDL implementation 455_x000D_
_x000D_
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20.3 ADSR core development 457_x000D_
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20.3.1 Register map 457_x000D_
_x000D_
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20.3.2 Wrapped ADSR circuit 458_x000D_
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20.4 ADSR driver 460_x000D_
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20.4.1 Class definition 460_x000D_
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20.4.2 Configuration methods 461_x000D_
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20.4.3 calc note freq() method 463_x000D_
_x000D_
_x000D_
20.4.4 play note() method 465_x000D_
_x000D_
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20.5 Test 465_x000D_
_x000D_
_x000D_
20.6 Project idea 466_x000D_
_x000D_
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20.7 Bibliographic notes 467_x000D_
_x000D_
_x000D_
20.8 Suggested experiments 467_x000D_
_x000D_
_x000D_
20.8.1 RTTTL music player 467_x000D_
_x000D_
_x000D_
20.8.2 ADSR envelope testing 467_x000D_
_x000D_
_x000D_
20.8.3 Pushbutton piano 467_x000D_
_x000D_
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20.8.4 Keyboard piano 468_x000D_
_x000D_
_x000D_
20.8.5 Keyboard recorder 468_x000D_
_x000D_
_x000D_
20.8.6 Real-time mode ADSR generator 468_x000D_
_x000D_
_x000D_
20.8.7 Real-time mode pushbutton piano 468_x000D_
_x000D_
_x000D_
20.8.8 Merged DDFS and ADSR core 468_x000D_
_x000D_
_x000D_
20.8.9 ADSR core with an automatic play FIFO buffer 468_x000D_
_x000D_
_x000D_
20.8.10 ADSR core for frequency modulation 468_x000D_
_x000D_
_x000D_
PART IV EMBEDDED SOC III: VIDEO CORES_x000D_
_x000D_
_x000D_
21 Introduction to the Video System 471_x000D_
_x000D_
_x000D_
21.1 Introduction to a video display 471_x000D_
_x000D_
_x000D_
21.1.1 Conceptual video display 471_x000D_
_x000D_
_x000D_
21.1.2 VGA interface 472_x000D_
_x000D_
_x000D_
21.2 Stream interface 473_x000D_
_x000D_
_x000D_
21.2.1 Random-access interface versus stream interface 473_x000D_
_x000D_
_x000D_
21.2.2 Flow control of the stream interface 473_x000D_
_x000D_
_x000D_
21.3 VGA synchronization 475_x000D_
_x000D_
_x000D_
21.3.1 Basic operation of a CRT monitor 475_x000D_
_x000D_
_x000D_
21.3.2 Horizontal synchronization 476_x000D_
_x000D_
_x000D_
21.3.3 Vertical synchronization 478_x000D_
_x000D_
_x000D_
21.3.4 Pixel clock rate 479_x000D_
_x000D_
_x000D_
21.3.5 VGA synchronization circuit 480_x000D_
_x000D_
_x000D_
21.4 Bar test-pattern generator 483_x000D_
_x000D_
_x000D_
21.5 Color-to-grayscale conversion circuit 485_x000D_
_x000D_
_x000D_
21.6 Demo video system 486_x000D_
_x000D_
_x000D_
21.7 Advanced video standards 488_x000D_
_x000D_
_x000D_
21.8 Bibliographic notes 489_x000D_
_x000D_
_x000D_
21.9 Suggested experiments 489_x000D_
_x000D_
_x000D_
21.9.1 Horizontal bar test-pattern generator 489_x000D_
_x000D_
_x000D_
21.9.2 Color channel selection circuit 489_x000D_
_x000D_
_x000D_
21.9.3 Enhanced color-to-grayscale conversion circuit 489_x000D_
_x000D_
_x000D_
21.9.4 Square test-pattern generator: part I 489_x000D_
_x000D_
_x000D_
21.9.5 Square test-pattern generator: part II 489_x000D_
_x000D_
_x000D_
21.9.6 Square test-pattern generator: part III 490_x000D_
_x000D_
_x000D_
21.9.7 Square test-pattern generator: part IV 490_x000D_
_x000D_
_x000D_
22 FPro Video Subsystem 491_x000D_
_x000D_
_x000D_
22.1 Organization of the video subsystem 491_x000D_
_x000D_
_x000D_
22.1.1 Overview 491_x000D_
_x000D_
_x000D_
22.1.2 Video controller 493_x000D_
_x000D_
_x000D_
22.1.3 HDL of the video controller 494_x000D_
_x000D_
_x000D_
22.2 FPro video IP core 495_x000D_
_x000D_
_x000D_
22.2.1 Basic functionality 495_x000D_
_x000D_
_x000D_
22.2.2 Blending operation 496_x000D_
_x000D_
_x000D_
22.2.3 Core architecture 498_x000D_
_x000D_
_x000D_
22.2.4 Alternative core partition 500_x000D_
_x000D_
_x000D_
22.3 Example video cores 500_x000D_
_x000D_
_x000D_
22.3.1 Bar test-pattern generator core 500_x000D_
_x000D_
_x000D_
22.3.2 Color-to-grayscale conversion core 503_x000D_
_x000D_
_x000D_
22.3.3 "Dummy" core 504_x000D_
_x000D_
_x000D_
22.4 FPro video synchronization core 504_x000D_
_x000D_
_x000D_
22.4.1 Line buffer 505_x000D_
_x000D_
_x000D_
22.4.2 Enhanced video synchronization circuit 508_x000D_
_x000D_
_x000D_
22.4.3 HDL code 511_x000D_
_x000D_
_x000D_
22.5 Daisy video subsystem 512_x000D_
_x000D_
_x000D_
22.5.1 Subsystem overview 512_x000D_
_x000D_
_x000D_
22.5.2 Interface to the video synchronization core 513_x000D_
_x000D_
_x000D_
22.5.3 HDL code 513_x000D_
_x000D_
_x000D_
22.5.4 Timing and performance considerations 517_x000D_
_x000D_
_x000D_
22.6 Vanilla daisy FPro system 517_x000D_
_x000D_
_x000D_
22.6.1 Clock management core 518_x000D_
_x000D_
_x000D_
22.6.2 Updated chu_io_map.svh 519_x000D_
_x000D_
_x000D_
22.6.3 HDL code 519_x000D_
_x000D_
_x000D_
22.7 Video driver and test program 521_x000D_
_x000D_
_x000D_
22.7.1 Updated chu_io_map.h and chu_io_rw.h files 521_x000D_
_x000D_
_x000D_
22.7.2 GPV core driver 522_x000D_
_x000D_
_x000D_
22.7.3 Test program 523_x000D_
_x000D_
_x000D_
22.8 Bibliographic notes 524_x000D_
_x000D_
_x000D_
22.9 Suggested experiments 525_x000D_
_x000D_
_x000D_
22.9.1 Color channel selection core 525_x000D_
_x000D_
_x000D_
22.9.2 Enhanced color-to-grayscale conversion core 525_x000D_
_x000D_
_x000D_
22.9.3 Square test-pattern generator core 525_x000D_
_x000D_
_x000D_
22.9.4 Alpha blending circuit 525_x000D_
_x000D_
_x000D_
22.9.5 "Highlight" core 525_x000D_
_x000D_
_x000D_
22.9.6 SVGA synchronization core 526_x000D_
_x000D_
_x000D_
22.9.7 Configurable video synchronization core 526_x000D_
_x000D_
_x000D_
22.9.8 Pipelined video subsystem 526_x000D_
_x000D_
_x000D_
23 Sprite Core 527_x000D_
_x000D_
_x000D_
23.1 Introduction 527_x000D_
_x000D_
_x000D_
23.2 Basic design 528_x000D_
_x000D_
_x000D_
23.2.1 Sprite RAM 528_x000D_
_x000D_
_x000D_
23.2.2 In-region comparison circuit 529_x000D_
_x000D_
_x000D_
23.3 Mouse pointer core 530_x000D_
_x000D_
_x000D_
23.3.1 Pointer sprite RAM 530_x000D_
_x000D_
_x000D_
23.3.2 Pixel generation circuit 531_x000D_
_x000D_
_x000D_
23.3.3 Top-level design 532_x000D_
_x000D_
_x000D_
23.4 "Ghost" character core 534_x000D_
_x000D_
_x000D_
23.4.1 Multiple images and animation 534_x000D_
_x000D_
_x000D_
23.4.2 Overview of the palette scheme 535_x000D_
_x000D_
_x000D_
23.4.3 Ghost sprite RAM and the palette circuit 535_x000D_
_x000D_
_x000D_
23.4.4 Animation timing circuit 537_x000D_
_x000D_
_x000D_
23.4.5 Pixel generation circuit 537_x000D_
_x000D_
_x000D_
23.4.6 Top-level design 540_x000D_
_x000D_
_x000D_
23.5 Sprite core driver and test program 541_x000D_
_x000D_
_x000D_
23.5.1 Sprite core driver 541_x000D_
_x000D_
_x000D_
23.5.2 Test program 543_x000D_
_x000D_
_x000D_
23.6 Bibliographic notes 544_x000D_
_x000D_
_x000D_
23.7 Suggested experiments 544_x000D_
_x000D_
_x000D_
23.7.1 Mouse pointer control with PS2 core 544_x000D_
_x000D_
_x000D_
23.7.2 Emulated ghost core 544_x000D_
_x000D_
_x000D_
23.7.3 Palette circuit for the mouse pointer sprite 544_x000D_
_x000D_
_x000D_
23.7.4 Sprite scaling circuit 544_x000D_
_x000D_
_x000D_
23.7.5 Portrait mode display 545_x000D_
_x000D_
_x000D_
23.7.6 Multiple-object generation 545_x000D_
_x000D_
_x000D_
23.7.7 Animation speed control 545_x000D_
_x000D_
_x000D_
23.7.8 Imitated blinking LED: part I 545_x000D_
_x000D_
_x000D_
23.7.9 Imitated blinking LED: part II 545_x000D_
_x000D_
_x000D_
23.7.10 Imitated blinking LED: part III 546_x000D_
_x000D_
_x000D_
24 On-Screen-Display Core 547_x000D_
_x000D_
_x000D_
24.1 Introduction to tile graphics 547_x000D_
_x000D_
_x000D_
24.2 Basic OSD design 549_x000D_
_x000D_
_x000D_
24.2.1 Text-mode display 549_x000D_
_x000D_
_x000D_
24.2.2 Font ROM 550_x000D_
_x000D_
_x000D_
24.2.3 Tile RAM 550_x000D_
_x000D_
_x000D_
24.2.4 Basic organization 551_x000D_
_x000D_
_x000D_
24.3 OSD core 552_x000D_
_x000D_
_x000D_
24.3.1 Font ROM 552_x000D_
_x000D_
_x000D_
24.3.2 Pixel generation circuit 553_x000D_
_x000D_
_x000D_
24.3.3 Top-level design 555_x000D_
_x000D_
_x000D_
24.4 OSD core driver and test program 557_x000D_
_x000D_
_x000D_
24.4.1 OSD core driver 557_x000D_
_x000D_
_x000D_
24.4.2 Testing program 558_x000D_
_x000D_
_x000D_
24.5 Bibliographic notes 559_x000D_
_x000D_
_x000D_
24.6 Suggested experiments 559_x000D_
_x000D_
_x000D_
24.6.1 Rotating banner 559_x000D_
_x000D_
_x000D_
24.6.2 Text console 559_x000D_
_x000D_
_x000D_
24.6.3 Underline for the cursor 559_x000D_
_x000D_
_x000D_
24.6.4 Portrait-mode display 560_x000D_
_x000D_
_x000D_
24.6.5 Font scaling circuit: part I 560_x000D_
_x000D_
_x000D_
24.6.6 Font scaling circuit: part II 560_x000D_
_x000D_
_x000D_
24.6.7 Extended font 560_x000D_
_x000D_
_x000D_
24.6.8 Tile-based ghost core 560_x000D_
_x000D_
_x000D_
25 VGA Frame Buffer Core 561_x000D_
_x000D_
_x000D_
25.1 Overview 561_x000D_
_x000D_
_x000D_
25.2 Frame buffer core 562_x000D_
_x000D_
_x000D_
25.2.1 FPGA memory consideration 562_x000D_
_x000D_
_x000D_
25.2.2 Video memory module 562_x000D_
_x000D_
_x000D_
25.2.3 Address translation 563_x000D_
_x000D_
_x000D_
25.2.4 Pixel generation circuit 564_x000D_
_x000D_
_x000D_
25.2.5 Register map 566_x000D_
_x000D_
_x000D_
25.2.6 Top-level HDL code 566_x000D_
_x000D_
_x000D_
25.3 Driver and test program 567_x000D_
_x000D_
_x000D_
25.3.1 Frame buffer core driver 567_x000D_
_x000D_
_x000D_
25.3.2 Geometrical modeling 568_x000D_
_x000D_
_x000D_
25.3.3 Test program 570_x000D_
_x000D_
_x000D_
25.4 Project ideas 570_x000D_
_x000D_
_x000D_
25.5 Bibliographic notes 572_x000D_
_x000D_
_x000D_
25.6 Suggested experiments 572_x000D_
_x000D_
_x000D_
25.6.1 Virtual prototyping board panel 572_x000D_
_x000D_
_x000D_
25.6.2 Virtual analog wall clock 572_x000D_
_x000D_
_x000D_
25.6.3 Geometrical model functions 572_x000D_
_x000D_
_x000D_
25.6.4 Simulated "Etch a Sketch" toy 572_x000D_
_x000D_
_x000D_
25.6.5 Frame buffer core with 3-bit color depth 573_x000D_
_x000D_
_x000D_
25.6.6 Frame buffer core with 1-bit color depth 573_x000D_
_x000D_
_x000D_
25.6.7 QVGA frame buffer core 573_x000D_
_x000D_
_x000D_
25.6.8 Line drawing hardware accelerator 573_x000D_
_x000D_
_x000D_
25.6.9 Bidirectional frame buffer access: part I 573_x000D_
_x000D_
_x000D_
25.6.10 Bidirectional frame buffer access: part II 573_x000D_
_x000D_
_x000D_
PART V EPILOGUE_x000D_
_x000D_
_x000D_
26 What's Next 577_x000D_
_x000D_
_x000D_
References 581_x000D_
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_x000D_
Appendix A: Tutorials 585_x000D_
_x000D_
_x000D_
A.1 Overview of Xilinx Vivado IDE 585_x000D_
_x000D_
_x000D_
A.2 Short tutorial on Vivado hardware development 589_x000D_
_x000D_
_x000D_
A.2.1 Create a design project 590_x000D_
_x000D_
_x000D_
A.2.2 Add or create Xilinx IP core instances 591_x000D_
_x000D_
_x000D_
A.2.3 Add or create HDL design files 591_x000D_
_x000D_
_x000D_
A.2.4 Add a constraint file 592_x000D_
_x000D_
_x000D_
A.2.5 Perform synthesis, implementation, and bitstream generation 593_x000D_
_x000D_
_x000D_
A.2.6 Program an FPGA device 593_x000D_
_x000D_
_x000D_
A.3 Short tutorial on Vivado simulation 594_x000D_
_x000D_
_x000D_
A.3.1 Add or create HDL testbench 596_x000D_
_x000D_
_x000D_
A.3.2 Perform initial simulation 596_x000D_
_x000D_
_x000D_
A.3.3 Customize waveform display 597_x000D_
_x000D_
_x000D_
A.4 Tutorial on IP instantiation 597_x000D_
_x000D_
_x000D_
A.4.1 Dual-clock FIFO core via HDL templates 598_x000D_
_x000D_
_x000D_
A.4.2 IP Catalog utility 599_x000D_
_x000D_
_x000D_
A.4.3 Generate a MicroBlaze MCS component 600_x000D_
_x000D_
_x000D_
A.4.4 XADC IP core 601_x000D_
_x000D_
_x000D_
A.4.5 Clock management IP core 602_x000D_
_x000D_
_x000D_
A.5 Short tutorial on FPro system development 604_x000D_
_x000D_
_x000D_
A.5.1 Derive FPro system hardware 605_x000D_
_x000D_
_x000D_
A.5.2 Export hardware configuration 605_x000D_
_x000D_
_x000D_
A.5.3 Derive software 605_x000D_
_x000D_
_x000D_
A.5.4 Embed elf file into FPGA's memory module and regenerate bitstream 608_x000D_
_x000D_
_x000D_
A.5.5 Set up the terminal emulator program 610_x000D_
_x000D_
_x000D_
A.5.6 Program an FPGA device 610_x000D_
_x000D_
_x000D_
A.6 Bibliographic notes 611_x000D_
_x000D_
_x000D_
Topic Index 613_x000D_
show more