Description
Springer Static Crosstalk-Noise Analysis For Deep Sub-Micron Digital Designs 2004 Edition by Pinhong Chen Desmond A. Kirkpatrick Kurt Keutzer
As the feature size decreases in deep sub-micron designs coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditionally static timing analysis tools have ignored cross coupling effects between wires altogether. Newer tools simply approximate the coupling capacitance by a 2X Miller factor in order to compute the worst case delay. The latter approach not only reduces delay calculation accuracy but can also be shown to underestimate the delay in certain scenarios. This book describes accurate but conservative methods for computing delay variation due to coupling. Furthermore most of these methods are computationally efficient enough to be employed in a static timing analysis tool for complex integrated digital circuits. To achieve accuracy a more accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy a variety of mechanisms for pruning the search space are detailed including: -Spatial pruning - reducing aggressors to those in physical proximity -Electrical pruning - reducing aggressors by electrical strength -Temporal pruning - reducing aggressors using timing windows -Functional pruning - reducing aggressors by Boolean functional analysis. Table of contents : List of FiguresList of TablesPreface1: Introduction 1. Motivation1.1 Process Trends1.2 CMOS Circuitry2. Background and Crosstalk Effects2.1 Static Timing Analysis2.2 Crosstalk Effects2.3 Functional Failure2.4 Timing Variation3. Search Space Pruning3.1 Spatial Pruning3.2 Electrical Pruning3.3 Temporal Pruning3.4 Functional Pruning3.5 Problem Complexity v.s. Accuracy4. Overview 2: Miller Factor Computation for Coupling Delay 1. Introduction2. Gate Driving and Coupling Model2.1 Nonlinearity of Driver Model 2.2 Driver Modeling3. Decoupling Approximation3.1 Coupling Model3.1.1 Bounds3.2 Simple Iterative Approach3.2.1 Convergence of the Simple Iterative Approach 3.3 Newton-Raphson Iteration for Miller Factor3.4 Multiple Miller Factors for Multiple Coupling Nets3.5 Slew Rate (Transition Time) Calculation4. Nonzero Initial Voltage Correction4.1 Glitch Waveform Approximation5. Experimental Results6. Review of Conservativism 7. Conclusion3: Convergence of Switching Window Computation1. Introduction2. Background2.1 Simple Upper and Lower Bounds for Switching Windows3. Fixed Point Computation3.1 Formulation 3.2 Fixed Point Iteration for Switching Windows Computation3.3 Multiple Convergence Points and Unstable Fixed Point3.4 Tightening Bounds4. Coupling Models4.1 Noise Calculation Model4.2 Switching Windows Overlapping Model4.3 Discontinuity in Discrete Models4.4 Error Bound between Discrete and Continuous Models4.5 Non-Monotone Property5. Convergence of Switching Windows Computation5.1 Proof of Convergence5.2 Computational Complexity5.3 Convergence Rate5.4 Least Evaluation of Coupling RC Networks5.5 Speed-up of Convergence6. Conclusion4: Speeding-Up Switching Window Computation1. Introduction2. Background and Definitions2.1 Piecewise Linear Waveform3. Multiple Aggressor Alignment Problem4. Coupling Delay Computation in Presence of Crosstalk Noise4.1 Algorithm4.2 Convergence of Our Algorithm4.3 Properties of Our Algorithm 4.4 Event Pruning4.5 Scheduling Technique5. Experimental Results 6. Review of Conservativism7. Conclusion5: Refinement of Switching Windows1. Introduction2. Formulation and Algorithm2.1 Arrival Time Uncertainty in Interconnect2.2 Switching Window Density2.3 Input Timing Uncertainty2.4 Complexity2.5 Implementation Consideration3. Resolution and Truncation Errors4. Experimental Results5. Consideration of Slew Rates6. Property of Time Slots and Conservativism7. Conclusion6: Functional Crosstalk Analysis1. Introduction2. Approaches and Related Work3. Vector Pair Searching Algorithm3.1 Overview3.2 BCOP: Boolean Constrained Optimization Problem3.3 Constructing Circuit via SAT3.4 Maximum Noise under the Zero-Delay Model 3.5 Fixed Delay Circuit Construction via SAT 3.5.1 Using Timed Boolean Variables 3.5.2 Translation of Maximum Coupling Effects into an Objective Function 3.5.3 Boolean Constrained Optimization3.5.4 Discrete Required Time Analysis3.5.5 Structural Hashing3.5.6 Coarse Quantum Time3.5.7 Boolean Constraint Relaxation 4. Experimental Results 5. Future Work 6. Conservativism Consideration 7. Conclusions 7: ConclusionsReferences