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SystemVerilog for Verification A Guide to Learning the Testbench Language Features at Meripustak

SystemVerilog for Verification A Guide to Learning the Testbench Language Features by Chris Spear, Greg Tumbush , Springer

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  • General Information  
    Author(s)Chris Spear, Greg Tumbush
    PublisherSpringer
    ISBN9781489995001
    Pages464
    BindingPaperback
    LanguageEnglish
    Publish YearApril 2014

    Description

    Springer SystemVerilog for Verification A Guide to Learning the Testbench Language Features by Chris Spear, Greg Tumbush

    Based on the highly successful second edition, this extended edition of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. It contains materials for both the full-time verification engineer and the student learning this valuable skill._x000D__x000D_In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features, including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students' understanding of the material. Other features of this revision include:_x000D__x000D__x000D__x000D_New sections on static variables, print specifiers, and DPI from the 2009 IEEE language standard_x000D_Descriptions of UVM features such as factories, the test registry, and the configuration database_x000D_Expanded code samples and explanations _x000D_Numerous samples that have been tested on the major SystemVerilog simulators_x000D__x000D_SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers._x000D_ Table of contents :- _x000D_ Verification Guidelines.- Data Types.- Procedural Statements and Routines.- Connecting the Testbench and Design.- Basic OOP.- Randomization.- Threads and Interprocess Communication.- Advanced OOP and Testbench Guidelines.- Functional Coverage.- Advanced Interfaces.- A Complete SystemVerilog Testbench.- Interfacing with C/C++._x000D_



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