Description
PEARSON INDIA Vlsi Design Methodology Development, 1/E by Thomas Dillinger
As microelectronics engineers design complex chips using existing circuit libraries, they must ensure correct logical, physical, and electrical properties, and prepare for reliable foundry fabrication. VLSI Design Methodology Development focuses on the design and analysis steps needed to perform these tasks and successfully complete a modern chip design.
Microprocessor design authority Tom Dillinger carefully introduces core concepts, and then guides engineers through modeling, functional design validation, design implementation, electrical analysis, and release to manufacturing. Writing from the engineer's perspective, he covers underlying EDA tool algorithms, flows, criteria for assessing project status, and key tradeoffs and interdependencies. This fresh and accessible tutorial will be valuable to all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels."
Table of Content
"Preface TOPIC I: OVERVIEW OF VLSI DESIGN METHODOLOGY Chapter 1 Introduction Chapter 2 VLSI Design Methodology Chapter 3 Hierarchical Design Decomposition TOPIC II: MODELING Chapter 4 Cell and IP Modeling TOPIC III: DESIGN VALIDATION Chapter 5 Characteristics of Functional Validation Chapter 6 Characteristics of Formal Equivalency Verification TOPIC IV: DESIGN IMPLEMENTATION Chapter 7 Logic Synthesis Chapter 8 Placement Chapter 9 Routing TOPIC V: ELECTRICAL ANALYSIS Chapter 10 Layout Parasitic Extraction and Electrical Modeling Chapter 11 Timing Analysis Chapter 12 Noise Analysis Chapter 13 Power Analysis Chapter 14 Power Rail Voltage Drop Analysis Chapter 15 Electromigration (EM) Reliability Analysis Chapter 16 Miscellaneous Electrical Analysis Requirements TOPIC VI: PREPARATION FOR MANUFACTURING RELEASE AND BRING-UP Chapter 17 ECOs Chapter 18 Physical Design Verification Chapter 19 Design for Testability Analysis Chapter 20 Preparation for Tapeout Chapter 21 Post-Silicon Debug and Characterization (“Bring-up”) and Product Qualification Epilogue Index "
Salient Features
"• Reflect complexity, cost, resources, and schedules in planning a chip design project • Perform hierarchical design decomposition, floorplanning, and physical integration, addressing DFT, DFM, and DFY requirements • Model functionality and behavior, validate designs, and verify formal equivalency • Apply EDA tools for logic synthesis, placement, and routing • Analyze timing, noise, power, and electrical issues • Prepare for manufacturing release and bring-up, from mastering ECOs to qualification"