Description
Elsevier Skew-Tolerant Circuit Design by David Harris
As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues.
Chapter 1 - Introduction
Chapter 2 - Fundamental Concepts
Chapter 3 - IP Switching
Chapter 4 - Tag Switching
Chapter 5 - MPLS Core Protocols
Chapter 6 - Quality of Service
Chapter 7 - Constraint based routing
Chapter 8 - Virtual Private Networks