Description
BSP Books Verilog Hdl Synthesis A Practical Primer by Bhasker J
The book provides a thorough understanding of the basics of the Verilog language, both from the features point of view and its usage in modeling. A number of examples for each language construct is provided; in addition, examples are provided to illustrate how collectively constructs can be used to model hardware. The various modeling styles supported by Verilog HDL are described in detail. The book explains how stimulus and control can also be described using the same Verilog language, including response monitoring and verification. The syntax of many of the constructs are shown in an easy to read manner, sometimes although not complete. This is done purposely to help explain the construct. The complete syntax of constructs of the Verilog language is provided in an appendix for reference