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OXFORD UNIVERSITY PRESS Vhdl: Design Synthesis And Simulation by Debaprasad Das
VHDL: Design Synthesis and Simulation is a textbook designed to meet the requirements of undergraduate students of electrical engineering (EE) computer science and engineering (CSE) information technology (IT) and electronics and communication engineering (ECE). This book would be useful for postgraduate students studying the related course while it would also serve as an invaluable reference for practising engineers.
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